The following disclosure relates to electrical circuits and signal processing.
Digital circuits can use a central clock whose signal is distributed to multiple circuit components and allows the circuit components to operate synchronously. The clock signal is typically generated by an oscillator circuit, for example, a quartz crystal or RC oscillator circuit. In a wireless communications circuit (which may include analog and/or digital components), a clock signal from a local oscillator can be used to mix signals up to intermediate frequency (IF) and radio frequency (RF) bands.
Clock signals are conventionally distributed as voltages. A conventional clock signal typically alternates between a low voltage and a high voltage. A quick transition between the low voltage and the high voltage, which results in a sharp clock edge, is typically desirable. The frequency of the transitions between voltages determines the clock frequency.
In large integrated circuits, between integrated circuit chips, or in communications systems, the conduits along which a clock signal is transmitted can be long. A conduit typically has a parasitic capacitance that increases with the length of the conduit. The parasitic capacitance on long clock distribution conduits can be significant at the frequencies at which a modern clock can operate. As clock frequencies rise, detrimental effects of parasitic capacitance typically become more severe. The parasitic capacitance typically requires power to charge and discharge as the voltage on the conduit varies, thereby increasing the power used by a circuit. Charging and discharging the parasitic capacitance on a conventional clock distribution conduit typically slows the transition of the clock signal between the low voltage and the high voltage, resulting in a lower-quality clock signal. Voltage swings on a long conduit can capacitively couple to parts of a circuit to which the conduit is not connected, thereby introducing noise into the circuit from a clock signal on a conduit and into the clock signal from the circuit.
To mitigate the increased power consumption caused by parasitic capacitance and to sharpen clock edges, inductance can be added to a conventional clock distribution circuit. The amount of added inductance can be chosen so that the inductance in the conventional clock distribution circuit resonates with the parasitic capacitance at the clock frequency. When the inductance and the parasitic capacitance resonate, a high impedance is presented between the conduit and ground, reducing the power loss through the parasitic capacitance and sharpening the clock edge.
Monolithic inductors typically require a significant amount of area on an integrated-circuit chip. In addition, when process variations affect the amount of inductance or parasitic capacitance in a conventional clock distribution circuit, the resonant frequency of the inductance and parasitic capacitance can shift away from the clock frequency, degrading the clock signal and increasing power loss. The introduction of inductance into the clock distribution circuit typically decreases the bandwidth of the clock signal.